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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14520B See Page 6-292
MC14521B 24-Stage Frequency Divider
The MC14521B consists of a chain of 24 flip-flops with an input circuit that allows three modes of operation. The input will function as a crystal oscillator, an RC oscillator, or as an input buffer for an external oscillator. Each flip-flop divides the frequency of the previous flip-flop by two, consequently this part will count up to 224 = 16,777,216. The count advances on the negative going edge of the clock. The outputs of the last seven-stages are available for added flexibility. * All Stages are Resettable * Reset Disables the RC Oscillator for Low Standby Power Drain * RC and Crystal Oscillator Outputs Are Capable of Driving External Loads * Test Mode to Reduce Test Time * VDD and VSS Pins Brought Out on Crystal Oscillator Inverter to Allow the Connection of External Resistors for Low-Power Operation * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load over the Rated Temperature Range. MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter VDD Vin, Vout Iin, Iout PD Tstg DC Supply Voltage Value Unit V V L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII
- 0.5 to + 18.0 10 500 Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW - 65 to + 150
TA = - 55 to 125C for all packages.
PIN ASSIGNMENT
Q24 RESET VSS OUT 2 VDD IN 2 OUT 1 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q23 Q22 Q21 Q20 Q19 Q18 IN 1
_C
TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
RESET 2 Output Q18 Q19 Q20 Q21 Q22 Q23 Q24 Count Capacity 218 = 262,144 219 = 524,288 220 = 1,048,576 221 = 2,097,152 222 = 4,194,304 223 = 8,388,608 224 = 16,777,216
9 IN 1
6 IN 2
STAGES 1 THRU 17 VDD = PIN 16 VSS = PIN 8
STAGES 18 THRU 24 Q18 Q19 Q20 Q21 Q22 Q23 Q24
7 OUT 1
5 VDD
4 3 OUT2 VSS
10
11
12
13
14
15
1
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14521B 1
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source Pins 4 & 7 5.0 5.0 10 15 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 1.2 - 0.25 - 0.62 - 1.8 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 1.0 - 0.2 - 0.5 - 1.5 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 3.5 - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 0.7 - 0.14 - 0.35 - 1.1 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) Pins 1, 10, (VOH = 9.5 Vdc) 11, 12, 13, 14 (VOH = 13.5 Vdc) and 15 (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Sink mAdc Iin Cin IDD Adc pF Adc IT IT = (0.42 A/kHz) f + IDD IT = (0.85 A/kHz) f + IDD IT = (1.40 A/kHz) f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.003. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14521B 2
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Vdc 5.0 10 15 tPHL, tPLH 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 tWH(cl) 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- 385 150 120 -- -- -- -- -- -- 1400 600 450 30 0 - 40 1300 500 375 140 55 40 3.5 9.0 12 -- -- -- 700 300 225 - 200 - 160 - 110 2600 1000 750 -- -- -- 2.0 5.0 6.5 15 5.0 4.0 -- -- -- -- -- -- ns -- -- -- -- -- -- 4.5 1.7 1.3 6.0 2.2 1.7 9.0 3.5 2.7 12 4.5 3.5 ns Min -- -- -- Typ # 100 50 40 Max 200 100 80 s Unit ns Output Rise and Fall Time (Counter Outputs) tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns tTLH, tTHL Propagation Delay Time Clock to Q18 tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns tPHL, tPLH = (0.5 ns/pF) CL + 1275 ns Clock to Q24 tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns tPHL, tPLH = (0.66 ns/pF) CL + 2167 ns tPHL, tPLH = (0.5 ns/pF) CL + 1675 ns Propagation Delay Time Reset to Qn tPHL = (1.7 ns/pF) CL + 1215 ns tPHL = (0.66 ns/pF) CL + 467 ns tPHL = (0.5 ns/pF) CL + 350 ns Clock Pulse Width Clock Pulse Frequency fcl MHz Clock Rise and Fall Time tTLH, tTHL s Reset Pulse Width tWH(R) ns Reset Removal Time trem ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD 500 F VDD PULSE GENERATOR IN 2 0.01 F CERAMIC VDD Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS CL CL Vin 20 ns 90% 10% 50% DUTY CYCLE 20 ns VDD 0V ID CL CL CL CL CL 50% R VSS
Figure 1. Power Dissipation Test Circuit and Waveform
MOTOROLA CMOS LOGIC DATA
MC14521B 3
VDD VDD PULSE GENERATOR IN 2 VDD Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS CL IN 2 CL CL CL CL CL CL Qn 50% 10% tWL 90% 10% tPLH tTLH tPHL tTHL 20 ns 50% 20 ns 90% tWH 20 ns
R VSS
Figure 2. Switching Time Test Circuit and Waveforms
Characteristic Crystal Characteristics Resonant Frequency Equivalent Resistance, RS VDD Ro VDD R* VDD External Resistor/Capacitor Values Ro CT CS Frequency Stability Frequency Change as a Function of VDD (TA = 25_C) VDD Change from 5.0 V to 10 V VDD Change from 10 V to 15 V Frequency Change as a Function of Temperature (VDD = 10 V) TA Change from - 55_C to + 25_C MC14521 only Complete Oscillator* TA Change from +25_C to + 125_C MC14521 only Complete Oscillator*
500 kHz Circuit 500 1.0 47 82 20
50 kHz Circuit 50 6.2 750 82 20
Unit kHz k k pF pF
18 M
CS
CT
IN 1 OUT 1 OUT 2 Q18 Q19 IN 2 Q20 Q21 Q22 Q23 R Q24 VSS VSS R*
+ 6.0 + 2.0 - 4.0 + 100
+ 2.0 + 2.0 - 2.0 + 120
ppm ppm ppm ppm
* Optional for low power operation, 10 k R 70 k.
Figure 3. Crystal Oscillator Circuit
MC14521B 4
IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII
*Complete oscillator includes crystal, capacitors, and resistors.
- 2.0 - 160
- 2.0 - 560
ppm ppm
Figure 4. Typical Data for Crystal Oscillator Circuit
MOTOROLA CMOS LOGIC DATA
100 8.0 VDD = 15 V FREQUENCY DEVIATION (%) 4.0 0 -4.0 -8.0 -12 -16 -55
RTC = 56 k, C = 1000 pF
TEST CIRCUIT FIGURE 7
f, OSCILLATOR FREQUENCY (kHz)
50 20 10 5.0 2.0 1.0 0.5 0.2 f AS A FUNCTION OF C (RTC = 56 k) (RS = 120 k)
VDD = 10 V
TEST CIRCUIT FIGURE 7 f AS A FUNCTION OF RTC (C = 1000 pF) (RS 2RTC)
10 V
5.0 V
{
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
0.1 1.0 k 125 0.0001 10 k 100 k RTC, RESISTANCE (OHMS) 0.001 0.01 C, CAPACITANCE (F) 1.0 m 0.1
-25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C), DEVICE ONLY
Figure 5. RC Oscillator Stability
Figure 6. RC Oscillator Frequency as a Function of RTC and C
VDD VDD IN 1 Q18 Q19 Q20 Q21 IN 2 Q22 Q23 Q24 OUT 1 R OUT 2 VSS VSS
RS C
RTC
VDD
VDD
VDD
IN 1 OUT 1 OUT 2 Q18 Q19 IN 2 Q20 Q21 Q22 Q23 R Q24 VSS VSS
PULSE GENERATOR
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Figure 7. RC Oscillator Circuit Figure 8. Functional Test Circuit FUNCTIONAL TEST SEQUENCE
Inputs Reset 1 0 In 2 0 1 0 1 -- -- -- 1 0 0 1 1 0 Out 2 0 1 0 1 -- -- -- 1 0 0 0 0 1 1 1 1 VDD 1 1 0 Counter converted back to 24-stages in series mode. Out 2 converts back to an output. Counter ripples from an all "1" state to an all "0" stage. VSS VDD Outputs VDD Gnd Comments Q18 thru Q24 0 Counter is in three 8-stage sections in parallel mode Counter is reset. In 2 and Out 2 are connected together First "0" to "1" transition on In 2, Out 2 node. 255 "0" to "1" transitions are clocked into this In 2, Out 2 node. A test function (see Figure 8) has been included for the reduction of test time required to exercise all 24 counter stages. This test function divides the counter into three 8-stage sections, and 255 counts are loaded in each of the 8-stage sections in parallel. All flip-flops are now at a logic "1". The counter is now returned to the normal 24-stages in series configuration. One more pulse is entered into Input 2 (In 2) which will cause the counter to ripple from an all "1" state to an all "0" state. The 255th "0" to "1" transition. Gnd
MOTOROLA CMOS LOGIC DATA
MC14521B 5
LOGIC DIAGRAM
VDD 5 RESET 2
9 IN 1
1
2
STAGES 3 THRU 7
8
6 IN 2 7 OUT 1 3 VSS
4 OUT 2
9
10
STAGES 11 THRU 15
16
17
18
19
20
21
22
23
24
10 Q18
11 Q19
12 Q20
13 Q21
14 Q22
15 Q23
1 Q24
VDD = PIN 16 VSS = PIN 8
MC14521B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14521B 7
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14521B 8
*MC14521B/D*
MOTOROLA CMOS LOGIC DATA MC14521B/D

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